In the field of integrated circuits, a constant need is that of distributing the clock signal. As clock speeds have increased, the tolerances on clock skew have tightened.
A number of commercial products are on the market to assist in the design process. Cadence offers a program, Clock Tree Synthesis™, which generates a tree with limits on the size of a buffer and/or on the complexity of the floor plan that the tree can accommodate. Synopsis offers a program, Clock Tree Compiler™ that is generally similar.
IBM has a program, using a method described in U.S. Pat. No. 6,204,713, which can handle large buffers, which permits a tree with fewer levels.
The problem in generating clock trees can be described generally as striking a balance between delay, power consumed and ability to accommodate circuit blocks that have had their designs frozen. A short delay in the clock chain helps control skew. Low power is always desirable and the ability to reuse predesigned circuit blocks (embedded processors, RAMs, I/O, etc.) without redoing the layout to accommodate the clock saves greatly on cost in developing an ASIC.